Research Interests:
VLSI EDA (Physical Design Automation), ML approaches in VLSI Physical Design Automation, Low Power IC Design for ML HW Accelerators
VLSI EDA (Physical Design Automation), ML approaches in VLSI Physical Design Automation, Low Power IC Design for ML HW Accelerators
Recent Publications:
2. Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu, “ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, Issue 3, pp. 913-926 (March 2020).
2. Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Arindam Basu, “ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing”, Proceedings of 24th Asia and South Pacific Design Automation Conference (ASP- DAC), pp. 597-602, 2019.
3. Mohendra Roy, Sumon Kumar Bose, Bapi Kar, Pradeep Kumar Gopalakrishnan, Arindam Basu, “A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring”, Proceedings of IEEE Symposium Series on Computational Intelligence (SSCI), pp. 1501-1507, 2018.
4. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “An Early Global Routing Framework for Uniform Wire Distribution in SoCs”, Proceedings of International System-On-Chip Conference (SOCC), pp. 139-144, 2016.
5. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “A Novel EPE aware Hybrid Global Route Planner after Floorplanning”, Proceedings of International Conference on VLSI Design (VLSID), pp. 595-596, 2016.
6. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “A New Method for Defining Monotone Staircases in VLSI Floorplans”, Proceedings of International Symposium on VLSI (ISVLSI), pp. 107-112, 2015.
7. Sumit Saha, Bapi Kar, and Susmita Sur-Kolay, “A novel architecture for QPSK modulation based on time-mode signal processing”, Proceedings of International Symposium on VLSI Design and Test (VDAT), pp. 1-6, 2014.
8. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “Global Routing using Monotone Staircases with Minimal Bends”, Proceedings of International Conference on VLSI Design (VLSID), pp. 369-374, 2014.
9. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “STAIRoute: Global Routing using Monotone Staircase Channels”, Proceedings of International Symposium on VLSI (ISVLSI), pp. 90-95, 2013.
10. Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan and Chittaranjan Mandal, “A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans using Monotone Staircase Cuts”, Proceedings of VDAT 2012, Lecture Notes in Computer Science (LNCS), Vol. 7373, pp. 327-336, 2012.
2. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model”, Arxiv.org 2018 (https://arxiv.org/abs/1810.12789).
3. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning”, Arxiv.org 2018 (https://arxiv.org/abs/1811.05161).
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Journal Articles:
1. Bapi Kar, Pradeep Kumar Gopalakrishnan, Sumon Kumar Bose, Mohendra Roy, Arindam Basu, “ADIC: Anomaly Detection Integrated Circuit in 65-nm CMOS Utilizing Approximate Computing”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 28, Issue 12, pp. 2518-2529 (December 2020)2. Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Lei Zhang, Aakash Patil, Arindam Basu, “ADEPOS: A Novel Approximate Computing Framework for Anomaly Detection Systems and its Implementation in 65-nm CMOS”, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, Issue 3, pp. 913-926 (March 2020).
Conference Papers:
1. Pradeep Kumar Gopalakrishnan, Bapi Kar, Sumon Kumar Bose, Mohendra Roy, Arindam Basu, “Live Demonstration: Autoencoder-Based Predictive Maintenance for IoT”, International Symposium on Circuits and Systems (ISCAS), 2019.2. Sumon Kumar Bose, Bapi Kar, Mohendra Roy, Pradeep Kumar Gopalakrishnan, Arindam Basu, “ADEPOS: anomaly detection based power saving for predictive maintenance using edge computing”, Proceedings of 24th Asia and South Pacific Design Automation Conference (ASP- DAC), pp. 597-602, 2019.
3. Mohendra Roy, Sumon Kumar Bose, Bapi Kar, Pradeep Kumar Gopalakrishnan, Arindam Basu, “A Stacked Autoencoder Neural Network based Automated Feature Extraction Method for Anomaly detection in On-line Condition Monitoring”, Proceedings of IEEE Symposium Series on Computational Intelligence (SSCI), pp. 1501-1507, 2018.
4. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “An Early Global Routing Framework for Uniform Wire Distribution in SoCs”, Proceedings of International System-On-Chip Conference (SOCC), pp. 139-144, 2016.
5. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “A Novel EPE aware Hybrid Global Route Planner after Floorplanning”, Proceedings of International Conference on VLSI Design (VLSID), pp. 595-596, 2016.
6. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “A New Method for Defining Monotone Staircases in VLSI Floorplans”, Proceedings of International Symposium on VLSI (ISVLSI), pp. 107-112, 2015.
7. Sumit Saha, Bapi Kar, and Susmita Sur-Kolay, “A novel architecture for QPSK modulation based on time-mode signal processing”, Proceedings of International Symposium on VLSI Design and Test (VDAT), pp. 1-6, 2014.
8. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “Global Routing using Monotone Staircases with Minimal Bends”, Proceedings of International Conference on VLSI Design (VLSID), pp. 369-374, 2014.
9. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “STAIRoute: Global Routing using Monotone Staircase Channels”, Proceedings of International Symposium on VLSI (ISVLSI), pp. 90-95, 2013.
10. Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan and Chittaranjan Mandal, “A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans using Monotone Staircase Cuts”, Proceedings of VDAT 2012, Lecture Notes in Computer Science (LNCS), Vol. 7373, pp. 327-336, 2012.
Others Papers:
1. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction”, Arxiv.org 2018 (https://arxiv.org/abs/1810.10412).2. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model”, Arxiv.org 2018 (https://arxiv.org/abs/1810.12789).
3. Bapi Kar, Susmita Sur-Kolay, and Chittaranjan Mandal, “Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning”, Arxiv.org 2018 (https://arxiv.org/abs/1811.05161).
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